1. Field of the Invention
The present invention relates to a semiconductor apparatus having a logic level decision circuit deciding the binary logic level of an input signal from the exterior or an input signal of the interior, and to an inter-semiconductor apparatus signal transmission system.
2. Description of the Related Art
The binary logic level of a signal processed at the interior of a digital semiconductor apparatus, such as a semiconductor memory apparatus, an MPU (Micro Processing Unit), or the like, is generally expressed by a voltage value. The binary logic level of a signal transmitted between these semiconductor apparatuses is expressed by a voltage value.
FIG. 1 shows one example of a conventional inter-semiconductor apparatus signal transmission system.
A plurality of semiconductor apparatuses 100 are provided at the signal transmission system. Address/data bus and control signal lines 11 are commonly connected to these plurality of semiconductor apparatuses 100. Moreover, a reference voltage Vref transmitted at a voltage supplying line 12 is commonly supplied to the respective semiconductor apparatuses 100. The reference voltage Vref has an intermediate value of the voltage of the logic “1” level and the voltage of the logic “0” level of a binary input signal.
FIG. 2 shows an input receiver provided in the respective semiconductor apparatuses 100 of FIG. 1. The input receiver 101 decides the logic level of an input signal Vin by using the reference voltage Vref. At this time, a malfunction easily arises as will be described hereinafter.
That is to say, in the semiconductor apparatus, due to the miniaturization and the high-integration of an MOS transistor provided at the interior thereof, the maximum value of the supplied voltage has been limited and has become small. Therefore, the power source voltage and the voltage difference of the two logic levels become small. As a result, the voltage difference between the reference voltage Vref, which is the intermediate value of the potentials of data “1” and data “0”, and the signal voltage of data “1” or data “0” which the input receiver receives become small.
In such a situation, if there are power source noise at the time of operation in the inner circuit of the semiconductor apparatus, fluctuations in the ground level, and swinging due to reflection or the like of the input signal itself, it is easy for the input receiver to malfunction. Further, the reference voltage Vref supplied from the exterior of the semiconductor apparatus fluctuates in accordance with the coupling with the adjacent wiring on a board or in a module in which the semiconductor apparatus is packed. Fluctuations of the reference voltage Vref are a factor of malfunctioning of the input receiver.
On the other hand, in a semiconductor memory which has a plurality of memory cells and which has one input/output port, a sense amplifier circuit deciding the logic level of a reading signal from a memory cell conventionally uses an intermediate value of the voltage corresponding to data “1” and the voltage corresponding to data “0”. In this case, if the reading signal has a small amplitude resulting from the weakness of the driving ability of the memory cell or the like, at the time of deciding it by the sense amplifier circuit, malfunctioning easily arises as described above.
That is to say, due to the semiconductor memory being made to be highly integrated and to have a large capacity, the load from the standpoint of the memory cell becomes large, and high-speed performance is also required. Therefore, there is the trend that the voltage difference between the input signal voltage received when the sense amplifier circuit starts the sensing operation and the reference voltage, or the current difference between the input signal current and the reference current, becomes small. This means that the number of memory cells whose data cannot be sensed increases if the sensitivity of the sense amplifier circuit does not vary in consideration of the manufacturing dispersion of the memory cells, and a deterioration of yield is brought about.
FIG. 3 and FIG. 4 respectively show specific examples of the conventional logic level decision circuit used as a sense amplifier circuit in the semiconductor memory.
In the logic level decision circuit, because an intermediate value of the reading current Iref1 or the reading voltage Vref1 from the memory cell of data “1” and the reading current Iref0 or the reading voltage Vref0 from the cell of data “0” is generated as a reference signal, the problems which were described above arise.
On the other hand, in recent years, a large number of elements storing data in accordance with new principles have been proposed. One of them is a magnetic tunnel junction (hereinafter, MTJ) which carries out storing of “1”/“0” data by using the tunneling magneto resistive effect. A magnetic random access memory (MRAM), in which a plurality of magnetic memory cells structured by using the MTJ elements are arranged in a matrix form and which has non-volatility and high-speed performance, has been proposed.
An MR ratio, which is an index in which a rate of change in the resistances of the MTJ element, i.e., the variation of the resistances of data “1” and “0”, is divided by the resistance in the “0” state, is about 20% to 40%. Accordingly, the difference between the signal level read from the MTJ element of data “1” and the signal level read from the MTJ element of data “0” is only about 20 percent to 30 percent.
Because the MTJ element is structured such that current flows via a tunnel barrier film, a relationship is established in which the change in the value of resistance of the MRJ element logarithmically increases in accordance with the increase of the film thickness of the tunnel barrier film. The film thickness of the tunnel barrier film of MTJ elements which are currently reported is about several nm, and the dispersion in the resistances between different MTJ elements is accelerated even more in accordance with the dispersion in the film thickness of the tunnel barrier film.
Accordingly, if a method, in which an intermediate level of data “1” and “0” is used as a reference voltage or a reference current which is input to a sense amplifier circuit, is used, when a signal difference becomes small due to the dispersion in the resistances of the MTJ element, a malfunction of reading is brought about, and deterioration of yield is brought about. From the standpoint of making the MRAM to have a large capacity, it is not preferable to form a structure in which two MTJ elements store one bit in order to prevent such a malfunction of reading.
As described above, the conventional logic level decision circuit used for an input receiver or a sense amplifier circuit has the problems that malfunctioning easily arises due to dispersion in the reference levels for detecting an input signal, and the like, and it is preferable to resolve such problems.